RISC-V System-on-Chip Design

RISC-V System-On-Chip Design fits at the nexus of computer architecture, microarchitecture, and chip design. It is written to be accessible to an advanced undergraduate audience with limited background. It explains concepts from operating systems, VLSI, and memory systems as necessary, and high school mathematics is sufficient preparation for most of the book, although the floating point and division chapters will be primarily of interest to those with a curiosity about computer arithmetic. Like Harris and Harris's Digital Design and Computer Architecture textbooks, this book will appeal to students with easy-to-read and complete explanations, sidebars, and occasional humor and cartoons.It comes with an open-source implementation and will include end-of-chapter problems to extend the RISC-V processor in various ways. Ancillary materials include a GitHub repository with complete open-source SystemVerilog code, validation code in C and assembly language, and code for benchmarking and booting Linux.Ancillary materials include a GitHub repository with complete open-source SystemVerilog code for the fully-functional Wally RISC-V SoC, validation code in C and assembly language, code for benchmarking and booting Linux, labs, slides, exercises, and figures.Please note that chapters 20-23 and Appendices A-D and F are not included in the print book but are available on the Companion Site athttps://shop.elsevier.com/books/book-companion/9780323994989. These chapters and appendices are also in the electronic version of the book.Supplementary resources for the book are also available on a website hosted by the authors at: ddcabook.com. Includes a concrete application & implementation of the open RISC-V architectureExplores rarely taught microarchitectural issues: Pipelines, buses, caches, branch prediction, virtual memory, floating-point, cryptography & peripheralsIllustrates system design with CORE-V Wally, a fully functional RISC-V system-on-chip: Programming & debugging RISC-V in C & assemblySystemVerilog design, debug, verification & synthesisBenchmarkingBooting Linux on a simulator & FPGAProvides complete open-source code: github.com/openhwgroup/cvw